The present invention relates to semiconductor devices and methods of manufacturing semiconductor devices, and more specifically relates to semiconductor devices in which NPN transistors and PNP transistors are formed on the same chip, to semiconductor devices in which such bipolar transistors and MOS transistors are formed on the same chip, and to methods for manufacturing such semiconductor devices.
One of the advantages of a bipolar device (BJT) to a MOS device is in its high-speed operation. It results from the property of high-speed response and high current-driving power of the bipolar transistor. However, the bipolar device has the disadvantage that it is not suited to large-scale integration.
The MOS device enables substantial reduction of electric power consumption by use of the CMOS structure in which both of NMOS transistors and PMOS transistors are formed on one chip instead of the old structure in which only one of them is formed on one chip.
On the other hand, in the field of bipolar devices, there is a growing need of a high-speed PNP transistor that can operate at a speed close to the operation speed of the ultra high-speed NPN transistor typified by the SiGe:HBT (hetero bipolar transistor having a SiGe layer for its base). That is because, if a complimentary circuit comprised of the ultra high-speed NPN transistor and the high-speed PNP transistor is formed on the same chip as an elementary circuit, it becomes possible to reduce sharply a current of the bipolar device, keeping its high-speed performance and high driving power or even reinforcing them, whereby a power supply of the bipolar device can be downsized, and an operational amplifier having an increased operation speed and a reduced power consumption can be realized, for example.
In addition, as the CMOS device becomes faster, the need of a faster LDVS (Low Voltage Differential Signaling) circuit having PNP transistors constituting an interface between the CMOS device and the bipolar device is growing recently. Thus the necessity of increasing the operation speed of the PNP transistor is arising in this respect as well.
However, forming the PNP transistor and the ultra high-speed NPN transistor which is typically a SiGe:HBT in one chip requires a very complicated manufacturing process including a number of process steps. To reduce the number of process steps, the structure of the PNP transistor has to be extremely simplified and accordingly its performance is substantially lowered.
Moreover, even if the PNP transistor and the NPN transistor are formed on the same chip through long and elongated process to constitute the complementary circuit, both its cut-off frequency and maximum oscillation frequency are on the order of 20 GHz which are lower than one-fifth those of the NPN transistor of the SiGe:HBT type. Accordingly, even if the bipolar device of the complementary type is realized by forming the NPN transistor and the PNP transistor in one and the same chip, its operation speed is limited to that of the PNP transistor although the cut-off frequency fT and the maximum oscillation frequency fmax of the NPN transistor thereof exceed 100 GHz.
Incidentally, a structure in which an NPN transistor and a PNP transistor are formed in the same substrate is known as disclosed, for example, in Japanese Patent Application No. 6-159732. In this structure, both of the NPN and PNP transistors are of the vertical type, and they take equal areas on the chip. This structure is symmetrical about conduction types (P-type and N-type) judging from the manufacturing process. Accordingly, the PNP transistor has operation speed, withstand voltage, and d.c. characteristics close to those of the NPN transistor, so this structure may be applicable to complementary circuits as well as power supplies. However, in this structure, since the base is formed by conventional ion implantation, even the NPN transistor will not have a maximum oscillation frequency over 50 GHz.
The present invention has been made in light of the foregoing problem with an object of manufacturing a semiconductor device in which the ultra high-speed NPN transistors and the high-speed PNP transistors are formed on the same chip without substantially increasing the number of process steps. Another object of the invention is to manufacture a semiconductor device in which high-speed PMOS transistors and NMOS transistors are formed in addition to the ultra high-speed NPN transistors and the high-speed PNP transistors in one and the same chip without substantially increasing the number of process steps.
The object of the invention is achieved also by a method of manufacturing a semiconductor device in which a vertical NPN transistor and a vertical PNP transistor are formed on the same substrate comprising:
a first step of forming a first oxide film, a P-polycrystal silicon film, and a second oxide film in succession on an N-silicon epitaxial film formed on a substrate;
a second step of making an opening in the first oxide film through which a surface of the N-silicon epitaxial film and a part of a bottom of the P-polycrystal silicon film are exposed by anaisotropically etching the second oxide film and the P-polycrystal silicon film, and then isotropically etching the first oxide film that has been exposed;
a third step of plugging at least a part of the opening by growing a selective epitaxial layer including a P-monocrystal layer from the surface of the N-silicon epitaxial film, and growing a polycrystal layer from the part of the bottom of the P-polycrystal silicon film; and
a fourth step of adjusting, within a PNP transistor section, a P-N junction""s position and impurity concentration by implanting or diffusing P-impurities into the N-silicon epitaxial layer in a self-aligning manner by use of the opening.
The object of the invention is also achieved by A method of manufacturing a semiconductor device in which a vertical NPN transistor and a vertical PNP transistor are formed on the same substrate comprising:
a first step of forming a P-epitaxial layer or a well layer for a PNP transistor section and forming an N-epitaxial layer or a well layer for a NPN transistor section on a substrate;
a second step of forming a first insulation film and a first polycrystal silicon in succession on the substrate on which the epitaxial layers or the well layers have been formed, separating the first polycrystal silicon layer into the PNP and NPN transistor sections by an exposure process and an etching process, and converting conduction type of the first polycrystal silicon layer into P-type for the NPN transistor section and into N-type for the PNP transistor section;
a third step of forming a second insulation film to cover an entire substrate surface and subsequently making an opening penetrating thorough the second insulation film and the first polycrystal silicon layer to expose the first insulation film in each of the NPN and PNP transistor sections;
a fourth step of etching isotropically first and then laterally the exposed first insulation film in the PNP transistor section with the NPN transistor section being protected by a resist pattern to expose a surface of the P-epitaxial layer or the well layer and a part of a bottom of the first polycrystal silicon layer, subsequently growing a selective epitaxial layer containing N-impurities within the opening, and thermally oxidizing a surface of the grown selective epitaxial layer; and
a fifth step of etching isotropically first and then laterally the exposed first insulation film in the NPN transistor section with the PNP transistor section being protected by a resist pattern to expose a surface of the N-epitaxial layer or the well layer and a part of a bottom surface of the first polycrystal silicon layer, subsequently growing a selective epitaxial layer containing P-impurities within the opening, and thermally oxidizing a surface of the grown selective epitaxial layer.
Another object of the invention is achieved by method of manufacturing a semiconductor device in which a vertical PNP transistor, a vertical NPN transistor, a lateral PMOS transistor and a lateral NMOS transistor are formed on the same substrate comprising:
a first step of forming a P-epitaxial layer for each of a PNP transistor section and an NMOS transistor section, and forming an N-epitaxial layer for each of an NPN transistor section and a PMOS transistor section on a substrate;
a second step of forming a first insulation film and a first polycrystal silicon layer in succession on the substrate on which the P-and N-epitaxial layers have been formed, separating the first polycrystal silicon layer into the NPN, PNP, PMOS, and NMOS transistor sections by an exposure process and an etching process, and converting conduction type of the first polycrystal silicon layer into P-type for the NPN and PMOS transistor sections and into N-type for the PNP and NMOS transistor sections;
a third step of forming a second insulation film to cover an entire substrate surface, and subsequently making an opening penetrating thorough the second insulation film and the first polycrystal silicon layer to expose the first insulation film in each of the NPN, PNP, PMOS and NMOS transistor sections;
a fourth step of etching isotropically first and then laterally the exposed first insulation film in each of the PMOS and NMOS transistor sections with the PNP and NPN transistor sections being protected by a resist pattern to expose surfaces of the P- or N-epitaxial layer and a part of a bottom of the first polycrystal silicon layer, subsequently growing a SiGe epitaxial layer that is lattice-relaxed with the P- or N-epitaxial layer and growing a silicon epitaxial layer that is not lattice-relaxed with the SiGe epitaxial layer within the opening, and then thermally oxidize a surface of the grown silicon epitaxial layer;
a fifth step of etching isotropically first and then laterally the exposed first insulation film in the PNP transistor section with the NPN, PMOS and PMOS transistor sections being protected by a resist pattern to expose surfaces of the P-epitaxial layer and a part of a bottom of the first polycrystal silicon layer, subsequently growing a selective epitaxial layer containing N-impurities within the opening, and thermally oxidizing a surface of the grown selective epitaxial layer;
a sixth step of etching isotropically first and then laterally the exposed first insulation film in the NPN transistor section with the PNP, PMOS and NMOS transistor sections being protected by a resist pattern to expose surfaces of the N-epitaxial layer and a part of a bottom of the first polycrystal silicon layer, subsequently growing a selective epitaxial layer containing P-impurities within the opening, and thermally oxidizing a surface of the grown selective epitaxial layer;
a seventh step of forming a third insulation film and a second polycrystal silicon layer in succession to cover the entire substrate surface, subsequently etching back the polycrystal silicon layer so that the polycrystal silicon layer remains as a sidewall of each of the openings, etching the third insulation film and an insulation film having been formed within each of the openings by using the remaining polycrystal silicon layer as a mask to expose a surface of the epitaxial layer within each of the openings, thermally oxidizing the exposed surface of the epitaxial layer thereby forming a gate oxide film for each of the PMOS and NMOS transistors, and implanting impurities into the PMOS and NMOS transistor sections for adjusting threshold voltages by use of a resist mask; and
an eighth step of removing the insulation films having been formed within the openings of the NPN and PNP transistor sections by use of a resist pattern, forming a third polycrystal silicon layer within each of the NPN, PNP, PMOS, and NMOS transistor sections, and converting conduction type of the third polycrystal silicon layer into N-type for the NPN and PMOS transistor sections and into P-type for the PNP and NMOS transistor sections.